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Semiconductor MS52C182A
DESCRIPTION
1998.6
Preliminary
65,536-Word X 16-Bit or 131,072-Word X 8-Bit STATIC RAM + 524,288-Word X 16-Bit or 1,048,576-Word X 8-Bit One Time PROM
The MS52C182A is a 65,536 -word by 16 -bit / 131,072-word by 8-bit electrically switchable 1Mb static RAM and 524,288-word by 16-bit / 1,048,576-word by 8-bit electrically switchable 8Mb One Time PROM featuring 2.7V to 3.6V power supply operation and direct LVTTL input / output compatibility. Since the circuitry is completely static,external clocks are unnecessary, making this device very easy to use. The MS52C182A is packaged in 44-pin plastic TSOP and 48-pin FBGA (9mmx10mm) ,suited for use in handy terminal and other application which required small space.
FEATURES * 65,536-word x 16-bit / 131,072-word x 8-bit configuration SRAM and 524,288-word x 16-bit / 1,048,576-word x 8-bit configuration OTP * Power supply voltage : 2.7 to 3.6V * Fully static operation * Operating temperature range : Ta= -20 to 70C * Access time : 100nS MAX (Vcc=2.7V) 80nS MAX (Vcc=3.0V) * Common address inputs and data inputs / outputs for SRAM and OTP * Input / Output LVTTL compatible * 3-state output * Data retention available at power supply voltage 1.5V for SRAM * Package options : 44-pin plastic TSOP (Type II) 48-pin plastic FBGA (TSOP44-P-400-0.8) (FBGA48-P-0910-0.8) (Product : MS52C182ATA) (Product : MS52C182ALA)
1
MS52C182A PIN CONFIGURATION (TOP VIEW)
A16 A15 A14 A13 A12 A11 A10 A9 CEs
1 2 3 4 5 6 7 8 9
44 A17 43 CEo 42 I/O15/A-1 41 I/O7 40 I/O14 39 I/O6 38 I/O13 37 I/O5 36 I/O12 35 I/O4 34 GND 33 VCC 32 I/O11 31 I/O3 30 I/O10 29 I/O2 28 I/O9 27 I/O1 26 I/O8 25 I/O0 24 OE 23 A18
BYTE/VPP 10 VCC 11 GND 12 WE 13 A8 14 A7 15 A6 16 A5 17 A4 18 A3 19 A2 20 A1 21 A0 22
44-pin TSOP (II)
2
MS52C182A PIN CONFIGURATION (TOP VIEW)
A B C D E F G H
6
A1
A4
A7
GND
VCC
A9
A12
A15
5
A0
A3
A6
WE BYTE/VPP A10
A13
A16
4
NC
A2
A5
A8
CEs
A11
A14
NC
3
NC
I/O0
I/O9
I/O3
I/O12
I/O6 I/O15/A-1 NC
2
A18
I/O8
I/O2
I/O11
I/O4
I/O13
I/O7
A17
1
OE
I/O1
I/O10
VCC
GND
I/O5
I/O14
CEo
48-pin FBGA
Pin Name A -1 - A15 A16 - A18 CEs CEo WE OE I/O0 - I/O15 VCC BYTE/VPP GND NC
Function Common Address Inputs Address Inputs for OTP Chip Enable for SRAM Chip Enable for OTP Write Enable for SRAM Common Output Enable Common Data Inputs / Outputs Common Power Supply Common Mode Switch & Program Power Supply for OTP Common Ground No Connection
3
MS52C182A
BLOCK DIAGRAM
VCC VPP GND
Column Decoder
A15 A16 A17 A18
Multiplexer
Column Decoder
. . . . . . . .
. . . . . . . .
Address Buffer
A-1 A0 A1 A2
Row Decoder
Row Decoder
SRAM Memory Array 64kw x 16b or 128kw x 8b
OTP Memory Array 512kw x 16b or 1Mw x 8b
Multiplexer
CEo
Control
CEs WE OE BYTE
Output Buffer ...... I/O0 I/O1 I/O2 I/O3 . . . . . . I/O12 I/O13 I/O14 I/O15
FUNCTION TABLE Operating Mode Standby 16-Bit SRAM Read 8-Bit SRAM Write 16-Bit 8-Bit 16-Bit OTP Read 8-Bit CEo CEs H H H H H H H H L L L L H H L L L L L L H H H H WE * * H H H H L L * * * * OE * * H L H L * * H L H L BYTE VCC / VPP H L H H L 2.7V L to H 3.6V L H H L L I/O0 - I/O7 High-Z High-Z High-Z DOUT High-Z DOUT DIN DIN High-Z DOUT High-Z DOUT I/O8 - I/O14 High-Z High-Z High-Z DOUT High-Z High-Z DIN High-Z High-Z DOUT High-Z High-Z I/O15 / A-1 High-Z * High-Z DOUT * L/H DIN L/H High-Z DOUT * L/H
Note : 1. * = Don't Care ("H" or "L") 2. It is forbidden to apply CEo="L" and CEs="L" simultaneously.
4
MS52C182A
FUNCTION TABLE (Continued) Operating Mode OTP Program OTP Program Inhibit OTP Program Verify CEo CEs L H H H H H WE * * * OE H H L BYTE VCC / VPP 9.75V 4.0V I/O0 - I/O7 DIN High-Z DOUT I/O8 - I/O14 DIN High-Z DOUT I/O15 / A-1 DIN High-Z DOUT
Note : 1. * = Don't Care ("H" or "L") 2. It is forbidden to apply CEo="L" and CEs="L" simultaneously.
ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Power Supply Voltage Input Voltage Output Voltage Power Dissipation Operating Temperature Storage Temperature Symbol VCC VPP VI VO PD Topr Tstg Condition Rating -0.5 to 5.0 -0.5 to 11.5 -0.5* to Vcc+0.5 -0.5* to Vcc+0.5 0.7 -20 to 70 -55 to 125 Unit V V V V W
C C
Respect to GND
Ta=25C
* -1.2VMin. for pulse width less than 30nS.
Recommended Operating Conditions Parameter Power Supply Voltage SRAM Data Retention Voltage Input High Voltage Input Low Voltage Symbol VCC VPP GND VCCH VIH VIL Vcc=2.7 to 3.6 Condition Min. 2.7 -0.5 0 1.5 2.2 -0.5* Typ.
(Ta= -20 to 70C) Max. 3.6 Vcc+0.5 0 3.6 Vcc+0.5 0.4 Unit V V V V V V
0
* -1.2VMin. for pulse width less than 30nS.
5
MS52C182A
DC Characteristics (1) Parameter Input Leakage Current Symbol Condition VIN=0 to VCC CEo=VIH , CEs=VIH or OE=VIH or WE=VIL VOUT=0 to VCC IOH=-500A IOL=2.1mA CEoVCC-0.2V CEsVCC-0.2V VIN=0 to VCC CEo=VIH CEs=VIH VIN=VIH or VIL CEo=VIH CEs=VIL OE=VIH VIN=VIH/VIL TCYC=100nS
(Vcc=3.0V0.3V,Ta=-20 to 70C) Min. -1.0 Typ. Max. 1.0 Unit A
ILI
Output Leakage Current
ILO
-1.0
1.0
A
Output High Voltage Output Low Voltage
VOH VOL
Vcc-0.5 0.4 10
V V A
ICCS Standby Power Supply Current ICCS1
0.3
mA
35
mA
ICCA
(SRAM) CEoVCC-0.2V
Operating Power Supply Current
CEs0.2V OEVCC-0.2V VIHVCC-0.2V VIL0.2V TCYC=1S CEo=VIL CEs=VIH OE=VIH VIN=VIH/VIL TCYC=100nS CEo0.2V CEsVCC-0.2V OEVCC-0.2V VIHVCC-0.2V VIL0.2V TCYC=1S BYTE/VPP=VCC
10
mA
35
mA
ICCA*
(OTP)
20
mA
VPP Power Supply Current * Read Current
IPP
10
A
6
MS52C182A
DC Characteristics (2) Parameter Input Leakage Current Symbol Condition VIN=0 to VCC CEo=VIH , CEs=VIH or OE=VIH or WE=VIL VOUT=0 to VCC IOH=-500A IOL=2.1mA CEoVCC-0.2V CEsVCC-0.2V VIN=0 to VCC CEo=VIH CEs=VIH VIN=VIH or VIL CEo=VIH CEs=VIL OE=VIH VIN=VIH/VIL TCYC=80nS
(Vcc=3.3V0.3V,Ta=-20 to 70C) Min. -1.0 Typ. Max. 1.0 Unit A
ILI
Output Leakage Current
ILO
-1.0
1.0
A
Output High Voltage Output Low Voltage
VOH VOL
Vcc-0.5 0.4 10
V V A
ICCS Standby Power Supply Current ICCS1
0.3
mA
40
mA
ICCA
(SRAM) CEoVCC-0.2V
Operating Power Supply Current
CEs0.2V OEVCC-0.2V VIHVCC-0.2V VIL0.2V TCYC=1S CEo=VIL CEs=VIH OE=VIH VIN=VIH/VIL TCYC=80nS CEo0.2V CEsVCC-0.2V OEVCC-0.2V VIHVCC-0.2V VIL0.2V TCYC=1S BYTE/VPP=VCC
15
mA
40
mA
ICCA*
(OTP)
25
mA
VPP Power Supply Current * Read Current
IPP
10
A
7
MS52C182A
SRAM AC Characteristics SRAM Read Cycle (1) Parameter Read Cycle Time Address Access Time CEs Access Time OE Access Time CEs to Output in Low-Z OE to Output in Low-Z Output Hold from Address Change CEs to Output in High-Z OE to Output in High-Z Symbol Condition (Vcc=3.0V0.3V,Ta=-20 to 70C)
tRC tAA tCO tOE tCLZ tOLZ tOH tCHZ tOHZ
Min. 100
Max. 100 100 50
10 5 10 35 35
Unit nS nS nS nS nS nS nS nS nS
SRAM Write Cycle (1) Parameter Write Cycle Time Address Setup Time Write Pulse Width Write Recovery Time Data Setup Time Data Hold Time WE to Output in High-Z CEs to End of Write Address Valid to End of Write Output Active from End of Write Symbol Condition
tWC tAS tWP tWR tDS tDH tWHZ tCW tAW tWLZ
(Vcc=3.0V0.3V,Ta=-20 to 70C) Min. Max. Unit 100 nS 0 nS 75 nS 0 nS 40 nS 0 nS 35 nS 90 nS 90 nS 5 nS
Test Condition Input Pulse Levels ------------------------- 0.4V/2.4V Input Timing Reference Levels --------- 0.8V/2.0V Output Load --------------------------------- 50pF Output Timing Reference Levels ------- 0.8V/2.0V Input Rise and Fall Time ----------------- 5nS
1.85V
690
Dout 50pF (Including scope and jig capacitance)
8
MS52C182A
SRAM Read Cycle (2) Parameter Read Cycle Time Address Access Time CEs Access Time OE Access Time CEs to Output in Low-Z OE to Output in Low-Z Output Hold from Address Change CEs to Output in High-Z OE to Output in High-Z Symbol Condition
(Vcc=3.3V0.3V,Ta=-20 to 70C)
tRC tAA tCO tOE tCLZ tOLZ tOH tCHZ tOHZ
Min. 80
Max. 80 80 40
10 5 10 30 30
Unit nS nS nS nS nS nS nS nS nS
SRAM Write Cycle (2) Parameter Write Cycle Time Address Setup Time Write Pulse Width Write Recovery Time Data Setup Time Data Hold Time WE to Output in High-Z CEs to End of Write Address Valid to End of Write Output Active from End of Write Symbol Condition
tWC tAS tWP tWR tDS tDH tWHZ tCW tAW tWLZ
(Vcc=3.3V0.3V,Ta=-20 to 70C) Min. Max. Unit 80 nS 0 nS 60 nS 0 nS 35 nS 0 nS 30 nS 70 nS 70 nS 5 nS
Test Condition Input Pulse Levels ------------------------- 0.4V/2.4V Input Timing Reference Levels --------- 0.8V/2.0V Output Load --------------------------------- 50pF Output Timing Reference Levels ------- 0.8V/2.0V Input Rise and Fall Time ----------------- 5nS
1.85V
690
Dout 50pF (Including scope and jig capacitance)
9
MS52C182A
SRAM Timing Diagrams SRAM Read Cycle (1) 16-bit Read Mode (BYTE=VIH)
tRC
A0 - A15
tAA tCO
CEs
tCHZ
tCLZ
OE
tOHZ
tOE
I/O0 - I/O15
tOH
Valid Data-Out
tOLZ
SRAM Read Cycle (2) 8-bit Read Mode (BYTE=VIL)
tRC
A-1 - A15
tAA tCO
CEs
tCHZ
tCLZ
OE
tOHZ
tOE
I/O0 - I/O7
tOH
Valid Data-Out
tOLZ
I/O8 - I/O15 High-Z High-Z
Notes : 1. A read cycle of SRAM occurs during the overlap of CEo="H", CEs="L", OE="L" and WE="H". 2.
tOHZ , tCHZ are specified by the time when DATA is floating , not defined by the output level.
10
MS52C182A SRAM Write Cycle (1) 16-bit Write Mode (BYTE=VIH)
tWC
A0 - A15
tCW
CEs
tAW
WE
tAS
tWP tDS
tWR tDH
Din (I/O0 - I/O15) Dout
Data-In
tWHZ
tWLZ
SRAM Write Cycle (2) 8-bit Write Mode (BYTE=VIL)
tWC
A-1 - A15
tCW
CEs
tAW
WE
tAS
tWP tDS
tWR tDH
Din (I/O0 - I/O7) Dout
Data-In
tWHZ
tWLZ
I/O8 - I/O15
High-Z
High-Z
11
MS52C182A
Notes : 1. A write cycle of SRAM occurs during the overlap of CEo="H" , CEs="L" and WE="L". 2. OE may be either of "H" or "L" in the write cycle of SRAM. 3. tAS is specified from CEs="L" or WE="L" , whichever occurs last. 4. tWP is an overlap time of CEs="L" and WE="L". 5. tWR , tDS , tDH are specified from CEs="H" or WE="H" , whichever occurs first. 6. tWHZ is specified by the time when DATA output is floating , not defined by the output level. 7. When I/O pins are in the output mode , don't apply the inverted input signal to the output pins.
SRAM Data Retention Characteristics Parameter
Data Retention Power Supply Voltage
(Ta=-20 to 70C) Min. 1.5 Typ. Max. Unit V
Symbol VCCH
Condition CEoVCC-0.2V CEsVCC-0.2V VIN=0 to VCC VCC=1.5V CEoVCC-0.2V CEsVCC-0.2V VIN=0 to VCC
Data Retention Power Supply Current
ICCH
3
A
Chip Deselect to Data Retention Time Operation Recovery Time
tCDR tR
0
nS
5
mS
tCDR
VCC 2.7V VIH VCCH CEs 0V
Data Retention Mode
tR
CEsVCC-0.2V
12
MS52C182A
OTP AC Characteristics (1) OTP Read Cycle (1) Parameter Read Cycle Time Address Access Time CEo Access Time OE Access Time CEo to Output in High-Z OE to Output in High-Z Output Hold from Address Change Symbol Condition CEo=OE=VIL OE=VIL CEo=VIL OE=VIL CEo=VIL CEo=OE=VIL (Vcc=3.0V0.3V,Ta=-20 to 70C)
tRC tAA tCO tOE tCHZ tOHZ tOH
Min. 100
Max. 100 100 50 40 35
0 0 0
Unit nS nS nS nS nS nS nS
OTP Read Cycle (2) Parameter Read Cycle Time Address Access Time CEo Access Time OE Access Time CEo to Output in High-Z OE to Output in High-Z Output Hold from Address Change Symbol Condition CEo=OE=VIL OE=VIL CEo=VIL OE=VIL CEo=VIL CEo=OE=VIL
(Vcc=3.3V0.3V,Ta=-20 to 70C)
tRC tAA tCO tOE tCHZ tOHZ tOH
Min. 80
Max. 80 80 50 40 35
0 0 0
Unit nS nS nS nS nS nS nS
Test Condition Input Pulse Levels ------------------------- 0.4V/2.4V Input Timing Reference Levels --------- 0.8V/2.0V Output Load --------------------------------- 50pF Output Timing Reference Levels ------- 0.8V/2.0V Input Rise and Fall Time ----------------- 5nS
1.85V
690 Dout 50pF (Including scope and jig capacitance)
13
MS52C182A
OTP Timing Diagrams OTP Read Cycle (1) 16-bit Read Mode (BYTE=VIH)
tRC
A0 - A18
tAA tCO
CEo
tCHZ
tOHZ
OE
tOE
I/O0 - I/O15
tOH
Valid Data-Out
OTP Read Cycle (2) 8-bit Read Mode (BYTE=VIL)
tRC
A-1 - A18
tAA tCO
CEo
tCHZ
tOHZ
OE
tOE
I/O0 - I/O7
tOH
Valid Data-Out
I/O8 - I/O15
High-Z
High-Z
Notes : 1. A read cycle of OTP occurs during the overlap of CEo="L", CEs="H" and OE="L". 2. tOHZ , tCHZ are specified by the time when DATA is floating , not defined by the output level.
14
MS52C182A
OTP DC Characteristics OTP Programming Operation Parameter Input Leakage Current Program Power Supply Current Power Supply Current Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Program Voltage VCC Voltage Symbol (Ta=25C5C)
ILI IPP2 ICC VIH VIH VOH VOL VPP VCC
Condition VI=VCC+0.5V CEo=VIL
Min.
Typ.
Max. 10 50 50 VCC+0.5 0.8 0.45 10.0 4.1
Unit A mA mA V V V V V V
IOH=-500A IOL=2.1mA
3.0 -0.5 2.4 9.5 3.9 9.75 4.0
OTP AC Characteristics (2) OTP Programming Operation Parameter Address Setup Time OE Setup Time Data Setup Time Address Hold Time Data Hold Time OE to Output in High-Z VPP Power Setup Time Program Pulse Width Data Valid from OE Symbol (Vcc=4.0V0.1V,VPP=9.75V0.25V,Ta=25C5C) Condition
tAS tOES tDS tAH tDH tDFP tVS tPW tOE
Min. 2 2 2 0 2 0 2 9
Typ.
Max.
130 10 11 150
Unit S S S S S nS S S nS
Pin Check Function Pin Check Function is to check contact between each device-pin and each socket-lead with EPROM programmer. Setting up address as the following condition call the preprogrammed codes on device outputs.
(Vcc=3.3V0.3V,CEo=VIL,BYTE/Vpp=VIH,Ta=25C5C) A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 DATA 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 VH* VH* 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 1 0 FF00 00FF
* :VH=8V
15
MS52C182A
OTP Programming Waveform
A0 - A18
tAS
CEo
tPW
tAH
tOES
OE
tDFP
tDS
I/O0 - I/O15 DIN
tDH tCE
DOUT
tVS
BYTE/Vpp
Program Program Verify
Note : When OTP is programming mode , CEs should be "H" level.
Capacitance Parameter Symbol Input Capacitance CIN1 CIN2 BYTE/VPP Capacitance Input/Output Capacitance CI/O Condition V I=0V VO=0V
(Vcc=3.3V , Ta=25C , f=1MHz) Min. Typ. Max. 10 60 10 Unit pF pF pF
Note : This parameter is periodically sampled and not 100% tested.
16
MS52C182A OTP Programming / Verify Flow Chart
Programming Verify Start Start NO Pin Check Bad Insertion NO Pin Check OK Address = First location VCC=3.0V VPP=3.0V NG OK Address = First location Bad Insertion
VCC=4.0V
VPP=9.75V
Verify (One Byte) PASS VCC=3.6V VPP=3.6V
Program 10s
Increment Address
NO Last Address ? YES Address = First location Verify (One Byte) PASS Device Passed X=0 Device Failed NG
NG Verify (One Byte) PASS NO Increment Address Last Address ? YES VCC=3.0V VPP=3.0V YES X=5? NO Program 10s X=X+1
NG Verify (One Byte) PASS Device Passed Device Failed
17
Semiconductor
NOTICE
The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-todate. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system orapplication that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents cotained herein may be reprinted or reproduced without our prior permission. All brand, company and product names are the trademarks or registered trademarks of their respective owners.
Copyright 1998 Oki Electric Industry Co., Ltd.
ADDRESSES & SEMICONDUCTOR WEB SITES
Ltd., OKI Electric Industry Co., Ltd. Device Business Group, 10-3, Shibaura, 4-chome, Minato-ku, Tokyo 108, Japan, Tel.: +81-(0)3-5445-6327, Fax.: +81-(0)3-5445-6328, http://www.oki.co.jp/OKI/DBG/english/index.htm (NOTE: URL is case sensitive) Group, OKI Semiconductor Group 785 North Mary Avenue, Sunnyvale, CA 94086, U.S.A., Tel.: +1-408-720-1900, Fax.: +1-408-720-1918, http://www.okisemi.com/ GmbH, OKI Electric Europe GmbH Head Office Europe, Hellersbergstrasse 2, D-41460 Neuss, Germany, Tel: +49-2131-15960, Fax: +49-2131-103539, http://www.oki-europe.de/ Ltd., OKI Electronics (Hong Kong) Ltd. Suite 1901-1&19, Tower 3, China Hong Kong City, 33 Canton Road, Tsimshatsui, Kowloon, Hong Kong, Tel.: +852-2-736-2336, Fax.: +852-2-736-2395 Ltd., OKI Semiconductor (Asia) Pte. Ltd. 78 Shenton Way 09-01, Singapore 0207, Tel.: +65-221-3722, Fax.: +65-323-5376 Ltd., OKI Semiconductor (Asia) Pte. Ltd. Taipei Branch, 7th Fl. No.260, Tun Hwa North Road, Taipei, Taiwan, R.O.C., Sumitomo-Flysun Building, Tel.: +886-2-2719-2561, Fax.: +886-2-2715-2892 http://www.oki.net.tw/
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